18EC72 VLSI Design VTU CBCS Notes
Here you can download the VTU 2018 Scheme notes, and Study materials of 18EC72 VLSI Design of the Electronics and Communications Engineering department.
University Name: Visvesvaraya Technological University (VTU), Belagavi
Branch Name: Electronics and Communication Engineering – ECE
Semester: 7th (4th Year BE)
Subject Code and Subject Name: 18EC72 VLSI Design
Scheme of Examination: 2018 Scheme
Marks Distribution: 40 Marks for Continuous Internal Assessment and 60 Marks for Semester end examination
Important Concepts discussed:
1st Module covers “A Brief History, MOS Transistors, CMOS Logic. Long-channel I-V Characteristics, Non-ideal I-V Effects, DC Transfer Characteristics.”
2nd Module covers “CMOS Fabrication and Layout, VLSI Design Flow, Introduction, CMOS Technologies, Layout Design Rules.”
3rd Module covers “Introduction, Circuit Design for Latches and Flip-Flops”
4th Module covers “Introduction, Basic Principles of Pass Transistor Circuits, Synchronous Dynamic Circuit Techniques, Dynamic CMOS Circuit Techniques.”
5th Module covers “Dynamic Random Access Memory (DRAM) and Static Random Access Memory. Logic Verification Principles, Manufacturing Test Principles, Design for testability”
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